ln order to form very large scale integration (VLSI) and ultra large scale integration (ULSI) chips, high density semiconductor devices, such as transistors, are required. Small, high density devices provide the added benefits of high speed and reduced parasitic capacitance and low resistance. However, shrinking device size places added demands on the alignment between the layers which form the device and device contacts, because alignment becomes more difficult as the device size shrinks.
The integrated circuit fabrication art has provided many "self-aligned" processes in an attempt to obtain small device size with small alignment tolerances. Self-aligned processes are described in U.S. Pat. No. 4,359,816 to Abbas et al. entitled Self-Aligned Metal Process For Field Effect Transistor Integrated Circuits; U.S. Pat. No. 4,378,627 to Jambotkar entitled Self-Aligned Metal Process For Field Effect Transistor Integrated Circuits Using Polycrystalline Silicon Gate Electrodes; and U.S. Pat. No. 4,517,729 to Batra entitled Method For Fabricating MOS Device With Self-Aligned Contacts.
One known process for fabricating high density devices with low parasitic resistance is the salicide or self-aligned silicide process, in which metal is deposited over a structure and reacted with the exposed silicon areas thereunder to form a silicide. In particular, to form Metal Oxide Semiconductor (MOS) field effect transistors, metal may be reacted with the exposed silicon areas of the source and drain as well as the exposed polysilicon areas of the gate to form a silicide. A gate sidewall oxide structure prevents the gate and source/drain areas from being electrically connected because of the lack of silicide formation on the oxide. Following silicide formation, a selective etch may remove the unreacted metal without attacking the silicide. The salicide process is generally described at pages 397-399 of Silicon Processing For The VLSI Era by S. Wolf and R. N. Tauber, Lattice Press, 1986. One particular example of a salicide process is illustrated in U.S. Pat. No. 4,641,417 to McDavid entitled Process For Making Molybdenum Gate and Titanium Silicide Contacted MOS Transistors In VLSI Semiconductor Devices, in which a molybdenum gate is protected from the salicide process by encapsulating with a cap oxide and sidewall oxide in order to seal the interface between the two oxides.
When practicing the salicide process, it is critical that the process itself does not degrade the favorable device characteristics which provide the high density structure. The salicide process can produce unacceptable changes in the device dimensions, which preclude formation of small, high density devices. Accordingly, much of the enhanced performance of the salicide process is lost. One example of this degradation is illustrated in a publication entitled A New Device Interconnect Scheme For Sub-Micron VLSI by D. C. Chen et al., IEDM 84, pages 118-121. In the Chen et al. publication a polysilicon gate is formed on the face of a silicon substrate. The polysilicon gate includes a sidewall oxide. Thin layers of refractory metal and amorphous silicon are then deposited sequentially in the same pumpdown. The amorphous silicon is then photolithographically defined and etched in a medium which has high selectivity to the underlying refractory metal. After resist strip the wafer is annealed, and the refractory metal reacts with the amorphous silicon as well as the monocrystalline silicon in the substrate to form a silicide. A selective wet etch removes the unreacted metal.
Unfortunately, the Chen et al. salicide process produces degraded devices in which the advantages of the salicide process are at least partially lost. Degraded devices are produced because the Chen et al. process requires a photoresist pattern which exposes the gate region. Due to alignment and lithographic tolerances, the photoresist cannot be patterned to abut the sidewall, so that an exposed region between the sidewall and photoresist contains refractory metal without amorphous silicon thereon. Then, during the silicide process, the exposed refractory metal between former edge the photoresist and the sidewall reacts with the silicon semiconductor substrate and consumes part of the silicon substrate. A multilevel silicide region is thereby formed in the source and drain regions, with part of the silicide being formed by consuming the amorphous silicon on the refractory metal and part of the silicide region being formed by consuming the underlying silicon substrate. However, by converting at least part of the underlying substrate to silicide, the characteristics of the substrate are altered. It is well known that in order to form small high density devices, very shallow device layers (e.g. source and drain regions) must be formed in the substrate. During the Chen salicide process, conversion of the substrate to salicide consumes at least a portion of the shallow device regions. In order to prevent consumption of a significant portion of the source/drain region, a deeper source/drain region must be provided. However, a deep source/drain region provides low density integrated circuit chips, thereby negating the advantage of the salicide process.